Metastability error detection and correction system and method for successive approximation analog-to-digital converters

摘要

A system and method are provided for the detection and correction of metastability errors in a successive approximation analog to digital converter (ADC). The successive approximation ADC (40) includes a comparator unit (424) that includes a NAND gate circuit (550) that outputs a comp_rdy_n signal when the comparator (500) has latched a result. ADC (40) includes a metastability detection and correction circuit (425) that includes a first logic circuit (700) that monitors the comp_rdy_n signal and detects a metastable event if that signal is not received within a portion of a conversion time period of the ADC. Responsive to detection of a metastable event, a second logic circuit (750) generates a correct conversion code at the output of the ADC. If no metastable event is detected during a conversion cycle of the ADC, the second logic circuit (750) outputs the conversion codes determined by the comparator (500).

主权项

1. A system for detection and correction of metastability errors in a conversion of a sampled analog signal by a successive approximation analog to digital converter coupled to a reference generator, the successive approximation analog to digital converter including a clock generator coupled to a successive approximation register and a logic state machine, and a digital to analog converter coupled to the successive approximation register, the logic state machine and the reference generator, the system comprising:
a comparator unit operatively coupled to the digital to analog converter and the sampled analog signal and having an output coupled to the successive approximation register, said comparator unit initiating a comparison of the sampled analog signal with a quantization level reference established by the digital to analog converter responsive to a comparator clocking signal, and after a time interval outputting a signal corresponding to said comparator unit latching a bit value respectively for each of a plurality of bit conversion states, said comparator unit outputting said latched bit value to the successive approximation register; and a metastability detection and correction circuit coupled to the successive approximation register, the logic state machine and the clock generator, said metastability detection and correction circuit being further coupled to said comparator unit for detecting a metastable event therein and outputting bit values received from the successive approximation register responsive to an absence of a metastable event and output of selected bit values responsive to detection of at least one metastable event within a processing cycle of the successive approximation analog to digital converter.