Device performing refresh operations of memory areas

摘要

Disclosed herein is a device that includes a plurality of memory circuits and a refresh control circuit configured to generate a plurality of refresh initiation signals such that one of the refresh initiation signals takes an active level. Each of the memory circuits comprises a memory cell array including a plurality of memory cells, at least one data terminal, a data read/write circuit performing a data read operation to read out read-data from a selected one of the memory cells and supply the read-data to the data terminal and a data write operation to receive write-data from the data terminal and write the write-data into a selected one of the memory cells, and a refresh circuit performing a data refresh operation on selected one or ones of the memory cells of the memory cell array in response to an associated one of the refresh initiation signals taking the active level.

主权项

1. A device comprising:
a plurality of memory areas operating independently of one another; a plurality of control circuits respectively controlling self-refresh operations of the memory areas independently and asynchronously; an oscillator outputting an oscillator signal having a first period; and a refresh start signal generation circuit generating a plurality of refresh start signals having a second period longer than the first period based on the oscillator signal, the refresh start signals having activation timings different from one another, wherein one of the memory areas corresponding to one of the control circuits that externally receives a self-refresh request is refreshed in response to an activation timing of a corresponding one of the refresh start signals.