Method and apparatus for reduced parasitics and improved multi-finger transistor thermal impedance

摘要

A transistor, a method and an apparatus for forming multiple connections to a transistor for reduced gate (FET/HEMT) or base (BJT/HBT) parasitics, and improved multi-finger transistor thermal impedance. Providing for a method and an apparatus that reduces a transistor's parasitics and reduces a transistor's thermal impedance, resulting in higher device bandwidths and higher output power. More particularly, providing for a method and an apparatus for applying compact, multiple connections to the gate of a FET (or HEMT) or the base of a BJT (or HBT) from many sides resulting in reduced parasitics and improved transistor thermal impedance.

主权项

1. A transistor for reduced device parasitics and improved thermal impedance, comprising:
a gate input terminal for receiving an input signal or current; a drain output terminal for outputting an output signal or current; a plurality of first metal layers positioned along a first x-y plane and including a metal layer connected to the gate input terminal and another metal layer connected to the drain output terminal; a plurality of first interconnect metal vias positioned below one or more of the plurality of first metal layers and connected to one or more of the plurality of first metal layers; a plurality of second metal layers positioned along a second x-y plane and below one or more of the plurality of first interconnect metal vias, and connected to one or more of the plurality of first interconnect metal vias; a plurality of second interconnect metal vias positioned below one or more of the plurality of second metal layers and connected to one or more of the plurality of second metal layers; a plurality of third metal layers positioned along a third x-y plane and below one or more of the plurality of second interconnect metal vias and connected to one or more of the plurality of second interconnect metal vias; a plurality of third interconnect metal vias positioned below one or more of the plurality of third metal layers and connected to one or more of the plurality of third metal layers; a plurality of fourth metal layers positioned along a fourth x-y plane and below one or more of the plurality of third interconnect metal vias and connected to one or more of the plurality of third interconnect metal vias; a plurality of fourth interconnect metal vias positioned below one or more of the plurality of fourth metal layers and connected to one or more of the plurality of fourth metal layers; one or more transistor metal layers positioned along a fifth x-y plane and below one or more of the fourth interconnect metal vias and connected to one or more of the fourth interconnect metal vias; a transistor semiconductor portion of the transistor connected to the one or more transistor metal layers; a transistor gate-contact metal positioned along a transistor gate x-y plane that is below one or more of the plurality of fourth interconnect metal vias, and connected to one or more of the plurality of fourth interconnect metal vias and the transistor semiconductor portion, the transistor gate-contact metal having a width along an x-axis and an opening; and a first metal gate finger positioned within the opening of the transistor gate-contact metal and spaced apart from the transistor gate-contact metal, the first metal gate finger having a width along an x-axis that is shorter than the width of the transistor gate-contact metal.