发明名称 Memory system and memory controller
摘要 A memory system according to the embodiment comprises a memory device including plural memory cells capable of storing d bits of data and operative to read/write data at every page; and a memory controller operative to control the memory device. The memory controller includes a page buffer operative to hold page data to be read from/written in a page of the memory device and send/receive the page data to/from the memory device, a data processing unit operative to detect and correct an error in the page data by processing target data in a finite field Zp modulo p generated based on the page data (p is a prime that satisfies 2<p<2d), and a mapping unit operative to execute mapping of the target data from the data processing unit as page data within the page buffer.
申请公布号 US8959415(B2) 申请公布日期 2015.02.17
申请号 US201113237418 申请日期 2011.09.20
申请人 Kabushiki Kaisha Toshiba 发明人 Toda Haruki
分类号 G11C29/00;G06F11/10;G11C11/56 主分类号 G11C29/00
代理机构 Oblon, Spivak, McClelland, Maier &amp; Neustadt, L.L.P. 代理人 Oblon, Spivak, McClelland, Maier &amp; Neustadt, L.L.P.
主权项 1. A memory controller for controlling a memory device, said memory device including plural memory cells capable of storing d bits of data, said d being an integer of 2 or more, in accordance with plural physical quantity levels and operative to read/write data at every page composed of specific bits in certain ones of said plural memory cells, wherein said memory controller, after reading data by said memory device, receives d pages at a time of page data stored in the same certain ones of said plural memory cells in said memory device, and then utilizes only the part corresponding to a p-value per data of d-bit, said p being a prime that satisfies 2<p<2d, as target data to detect and correct an error in said page data, each of bits of said data of d-bit being included in a different page.
地址 Tokyo JP