Providing a serial download path to devices

摘要

In one embodiment, an interface may include various mechanisms to handle incoming clock and data signals. More specifically, the interface includes a first multiplexer to receive a first data signal via a serial peripheral interface (SPI) bus coupled to a first pin and a second multiplexer to receive a first clock signal via the SPI bus coupled to a second pin of the first IC and a second clock signal via an inter-integrated circuit (I2C) bus coupled to a third pin. In addition, the interface may include a decoder to receive the second clock signal and a second data signal via the I2C bus coupled to a fourth pin.

主权项

1. An apparatus comprising:
a first integrated circuit (IC) including an interface having:
a first multiplexer to receive a first data signal via a serial peripheral interface (SPI) bus coupled to a first pin of the first IC;a second multiplexer to receive a first clock signal via the SPI bus coupled to a second pin of the first IC and a second clock signal via an inter-integrated circuit (I2C) bus coupled to a third pin of the first IC; anda decoder to receive the second clock signal and a second data signal via the I2C bus coupled to a fourth pin of the first IC, wherein the decoder is to cause the first multiplexer to output the first data signal responsive to an enable message for the SPI bus received via the I2C bus and otherwise to output a predetermined state signal, and to cause the second multiplexer to output the first clock signal responsive to the enable message.