发明名称 Method for fabricating package substrate
摘要 A package substrate includes a core layer, a first dielectric layer, a second circuit pattern, a first solder mask and an insulating layer. A first circuit pattern is disposed on a first surface of the core layer. The first dielectric layer covers the first circuit pattern. The second circuit pattern is located on the first dielectric layer and the second circuit pattern includes an interconnection circuit pattern within a chip mounting area. The first solder mask covers a portion of the second circuit pattern outside the chip mounting area. The insulating layer covers the chip mounting area and the interconnection circuit pattern. A plurality of embedded pads are located on an upper surface of the insulating layer.
申请公布号 US8955218(B2) 申请公布日期 2015.02.17
申请号 US201314073846 申请日期 2013.11.06
申请人 Unimicron Technology Corp. 发明人 Chen Tsung-Yuan;Cheng Shih-Lian
分类号 H01R9/00;H05K3/40;H01L23/498;H01L21/48;H05K3/46;H05K3/10;H01L23/00;H05K3/34 主分类号 H01R9/00
代理机构 代理人 Hsu Winston;Margo Scott
主权项 1. A method of fabricating a package substrate, comprising: providing a substrate comprising at least an inner-layer circuit pattern and at least an outer-layer circuit pattern, the outer-layer circuit pattern comprising an interconnect circuit pattern located within a chip mounting area; covering the substrate with a solder mask that covers the outer-layer circuit pattern; removing the solder mask from the chip mounting area to expose the interconnect circuit pattern; forming an insulation layer inside the chip mounting area to cover the interconnect circuit pattern; curing the insulation layer; and forming a plurality of embedded bond pads in a top surface of the insulation layer.
地址 Taoyuan TW