发明名称 |
Test pattern generation for semiconductor integrated circuit |
摘要 |
A test pattern is sequentially selected from an original test pattern sequence constituted by a plurality of test patterns including a don't care bit. Power consumption in each of regions obtained by substantially equally dividing a layout region of a semiconductor integrated circuit in a case where a don't care value is specified in the selected test pattern and this selected test pattern is applied to the semiconductor integrated circuit is estimated. A searching is conducted for a don't care value of the selected test pattern which minimizes a variation in power consumption among the regions by repeatedly changing the don't care value and repeatedly estimating power consumption in the regions. A new test pattern sequence constituted by a plurality of test patterns including no don't care bit is generated by defining the don't care value obtained by the searching as a don't care value of the selected test pattern. |
申请公布号 |
US8959001(B2) |
申请公布日期 |
2015.02.17 |
申请号 |
US201213550008 |
申请日期 |
2012.07.16 |
申请人 |
National University Corporation Nara Institute of Science and Technology;Kyushu Institute of Technology |
发明人 |
Inoue Michiko;Yoneda Tomokazu;Sato Yasuo |
分类号 |
G01R31/26;G01R31/3183;G01R31/3185;G01R31/317 |
主分类号 |
G01R31/26 |
代理机构 |
Studebaker & Brackett PC |
代理人 |
Studebaker & Brackett PC |
主权项 |
1. A test pattern generation method for a semiconductor integrated circuit subjected to scan design, the method comprising:
sequentially selecting, by using a computer, a test pattern from an original test pattern sequence constituted by a plurality of test patterns including a don't care bit; estimating power consumption in each of regions obtained by substantially equally dividing a layout region of the semiconductor integrated circuit in a case where a don't care value is specified in the selected test pattern and this selected test pattern is applied to the semiconductor integrated circuit; searching for a don't care value of the selected test pattern which minimizes a variation in power consumption among the regions by repeatedly changing the don't care value and repeatedly estimating power consumption in the regions; and generating a first new test pattern sequence constituted by a plurality of test patterns including no don't care bit by defining the don't care value obtained by the searching as a don't care value of the selected test pattern. |
地址 |
Nara JP |