发明名称 Image coding method, image coding apparatus, image decoding method and image decoding apparatus
摘要 An apparatus is provided for decoding last position information indicating a horizontal position and a vertical position of a last non-zero coefficient in a predetermined order within a current block to be decoded, the current block being included in a picture and including a plurality of coefficients. The apparatus includes one or more processors, a communication unit, and storage coupled to the one or more processors and the communication unit. The communication unit is configured to transmit a request for a bitstream to an external system, and receive the bitstream from the external system. The one or more processors are configured to obtain the bitstream, perform first arithmetic decoding, perform second arithmetic decoding, derive a horizontal component of the last position information, and derive a vertical component of the last position. A system for decoding and a displaying method are also provided.
申请公布号 US8958653(B2) 申请公布日期 2015.02.17
申请号 US201414157577 申请日期 2014.01.17
申请人 Panasonic Intellectual Property Corporation of America 发明人 Sasai Hisao;Nishi Takahiro;Shibahara Youji;Sugio Toshiyasu;Tanikawa Kyoko;Matsunobu Toru;Terada Kengo
分类号 G06K9/36;G06T9/00;G09G5/02;H04N1/405;H04N1/32;H04N1/41;H04N7/12;H04N11/02;H04N11/04;G06F15/00;G06F7/00;H04N19/593 主分类号 G06K9/36
代理机构 Greenblum & Bernstein, P.L.C. 代理人 Greenblum & Bernstein, P.L.C.
主权项 1. An apparatus for decoding last position information indicating a horizontal position and a vertical position of a last non-zero coefficient in a predetermined order within a current block to be decoded, the current block being included in a picture and including a plurality of coefficients, the apparatus comprising: one or more processors; a communication unit; and storage coupled to the one or more processors and the communication unit; wherein the communication unit is configured to: transmit a request for a bitstream to an external system; andreceive the bitstream from the external system; and wherein the one or more processors are configured to: obtain the bitstream including a first partial signal, a second partial signal, a third partial signal, and a fourth partial signal, in this order;perform first arithmetic decoding on a first partial signal and a third partial signal, respectively, to obtain a decoded first partial signal and a decoded third partial signal, wherein in the first arithmetic decoding, decoding is performed on the third partial signal when the first partial signal indicates a greater value than a predetermined value;perform second arithmetic decoding on a second partial signal and a fourth partial signal, respectively, to obtain a decoded second partial signal and a decoded fourth partial signal, the second arithmetic decoding being different from the first arithmetic decoding, wherein in the second arithmetic decoding, decoding is performed on the fourth partial signal when the second partial signal indicates a greater value than the predetermined value;derive a horizontal component of the last position information indicating the horizontal position of the non-zero coefficient from the decoded first partial signal and the decoded third partial signal; andderive a vertical component of the last position information indicating the vertical position of the non-zero coefficient from the decoded second partial signal and the decoded fourth partial signal.
地址 Torrance CA US