Number format pre-conversion instructions

摘要

Apparatus for processing data includes processing circuitry 16, 18, 20, 22, 24, 26 and decoder circuitry 14 for decoding program instructions. The program instructions decoded include a floating point pre-conversion instruction which performs round-to-nearest ties to even rounding upon the mantissa field of an input floating number to generate an output floating point number with the same mantissa length but with the mantissa rounded to a position corresponding to a shorter mantissa field. The output mantissa field includes a suffix of zero values concatenated the rounded value. The decoder for circuitry 14 is also responsive to an integer pre-conversion instruction to quantize and input integer value using round-to-nearest ties to even rounding to form an output integer operand with a number of significant bits matched to the mantissa size of a floating point number to which the integer is later to be converted using an integer-to-floating point conversion instruction.

主权项

1. Apparatus for processing data comprising:
processing circuitry configured to perform processing operations including floating point processing operations having 2N-bit floating point operands with an X-bit mantissa field and floating point processing operations having 2(N-2)-bit floating point operands with a Y-bit mantissa field, where N, X and Y are positive integers and X>Y; and decoder circuitry configured to decode program instructions to generate control signals to control said processing circuitry to perform said processing operations; wherein said decoder circuitry is configured to decode a floating point pre-conversion instruction to generate control signals to control said processing circuitry to perform a data processing operation to give a result the same as given by: receiving a 2N-bit input floating point operand having an X-bit input mantissa field; converting said X-bit input mantissa field to a Y-bit intermediate mantissa field with rounding using a round-to-nearest ties to even rounding mode; concatenating said Y-bit intermediate mantissa field with a suffix value comprising (X-Y) zeros to form an X-bit output mantissa field; and generating a 2N-bit output floating point operand having said X-bit output mantissa field.