3D semiconductor interposer for heterogeneous integration of standard memory and split-architecture processor

摘要

A standard memory chip (150) is vertically assembled with two processor chips (130, 140) of split architecture by means of a small silicon interposer (120) stacked onto a large silicon interposer (110); both interposers include through-silicon vias (TSVs), while the chips are free of TSVs. The TSVs of small interposer (120) connect to the memory chip (150) and to the bottom interposer (110). Symmetrically positioned relative to interposer (120), and connected to it by short signal traces, chips (130, 140) are attached to the TSVs of interposer 110, which in turn is attached to a substrate (160) with supply connections.

主权项

1. A semiconductor device comprising:
a first silicon interposer having a first and an opposite second surface and first through silicon vias TSVs extending through the first interposer from the first surface to the second surface, the first TSVs arrayed in a first, a second, and a third set; the first set located in a first interposer region and matching the terminals of a first semiconductor chip soldered to the first set, wherein the first semiconductor chip is vertically stacked upon the first surface of the first interposer, the first semiconductor chip together with the solder having a first height; the second set located in a second interposer region and matching the terminals of a second chip soldered to the second set, wherein the second semiconductor chip is vertically stacked upon the first surface of the first interposer, the second chip together with the solder having a second height; and the third set located between the first and second regions and matching the terminals of a second silicon interposer, the TSVs of the third set connected by conductive traces to TSVs of the first and the second sets; the second silicon interposer having a third surface and an opposite fourth surface and second TSVs extending through the second interposer from the third surface to the fourth surface, the third TSVs matching the terminals of a third semiconductor chip; the second interposer soldered to the third TSV set, wherein the second interposer is vertically stacked on the first interposer, the height of the second interposer together with the solder being at least as great as the first and the second heights; and the third semiconductor chip soldered to the second interposer, wherein the third semiconductor chip is vertically stacked upon the second interposer.