Low cost and high performance flip chip package

摘要

A low cost and high performance flip chip package is disclosed. By assembling the package using a substrate panel level process, a separate fabrication of a substrate is avoided, thus enabling the use of a coreless substrate. The coreless substrate may include multiple stacked layers of laminate dielectric films having conductive traces and vias. As a result, electrical connection routes may be provided directly from die contact pads to package contact pads without the use of conventional solder bumps, thus accommodating very high density semiconductor dies with small feature sizes. The disclosed flip chip package provides lower cost, higher electrical performance, and improved thermal dissipation compared to conventional fabricated substrates with solder bumped semiconductor dies.

主权项

1. A semiconductor package comprising:
a heat spreader having a recess, the recess defined by walls and an inner surface; a die disposed within the recess and attached to the walls and the inner surface by a die attachment material, the die having a plurality of die contact pads; a first dielectric layer over the heat spreader and the die, the first dielectric layer having a first plurality of vias coupled to the plurality of die contact pads; and a plurality of package contact pads coupled to the first plurality of vias such that the plurality of die contact pads are coupled to the plurality of package contact pads, wherein the plurality of package contact pads are disposed within a layer of solder resist over the first dielectric layer such that the plurality of package contact pads do not protrude beyond a top surface of the layer of solder resist, wherein the layer of solder resist and the plurality of package contact pads have a substantially similar thickness.