Data storage system and method for data migration between high-performance computing architectures and data storage devices using memory controller with embedded XOR capability

摘要

The present data storage system employs a memory controller with embedded logic to selectively XOR incoming data with data written in the memory to generate XOR parity data. The memory controller automatically performs XOR operations on incoming data based upon the address range associated with the memory “write” request. The system provides data migration and parity generation in a simple and effective manner and attains reduction in cost and power consumption. The memory controller may be built on the basis of FPGAs, thus providing an economical and miniature system.

主权项

1. A method for data migrating in a data storage system, comprising the steps of:
(a) embedding an XOR (Exclusive OR) logic function unit into a memory controller, thereby creating an XOR memory controller, wherein said XOR logic function unit includes a first buffer, a second buffer, and an XOR comparator coupled to said first and second buffers, (b) coupling said XOR memory controller between at least one host and a memory unit, (c) allocating a first memory address range and a second memory address range, (d) receiving a “write” data request from at least one host, said write data request having a requested address associated therewith, wherein said “write” data includes a first data block and at least one second data block, (e) decoding said requested address, (f) placing, under control of said XOR memory controller, said first data block into said first buffer at an address range corresponding to said first memory address range in accordance with said decoded requested address, (g) transferring, under control of said XOR memory controller, said first data block to an address range in said memory unit corresponding to said first memory address range, (h) placing, under control of said XOR memory controller, said at least one second data block into said first buffer at an address range corresponding to said second memory address range, (i) transmitting, under control of said XOR memory controller, said first data block from said memory unit into said second buffer, (j) applying, under control of said XOR memory controller, the XOR logic function to said first data block and said second data block written in said first and second buffers, respectively, thereby generating a first XOR result, and (k) placing, under control of said XOR controller, said first XOR result into said address range in said memory unit corresponding to said first memory address range.