| 发明名称 | Multiple clock domain debug capability | ||
| 摘要 | An integrated circuit with debug capability includes a first packer and synchronizer to combine a multiple number of values of a first trigger signal received from a first circuit to form a first packed trigger signal and to output a synchronized first packed trigger signal in response to a trigger clock signal, the first trigger signal being synchronous with a first source clock signal, a first logic gate to provide a first output trigger signal indicative of whether any of the first multiple number of values of the first trigger signal in the first synchronized packed trigger signal is in a first state, and a debug state machine responsive to the first output trigger signal to selectively provide a first action signal. | ||
| 申请公布号 | US8959398(B2) | 申请公布日期 | 2015.02.17 |
| 申请号 | US201213587631 | 申请日期 | 2012.08.16 |
| 申请人 | Advanced Micro Devices, Inc. | 发明人 | Nixon Scott P.;Rentschler Eric M. |
| 分类号 | G06F11/00 | 主分类号 | G06F11/00 |
| 代理机构 | Polansky & Associates, P.L.L.C. | 代理人 | Polansky & Associates, P.L.L.C. ;Polansky Paul J. |
| 主权项 | 1. An integrated circuit with multiple clock domain debug capability comprising: a first packer and synchronizer to combine a first plurality of values of a first trigger signal received from a first circuit to form a first packed trigger signal and to output a synchronized first packed trigger signal in response to a trigger clock signal, said first trigger signal being synchronous with a first source clock signal; a first logic gate to provide a first output trigger signal indicative of whether any of said first plurality of values of said first trigger signal in said first synchronized packed trigger signal is in a first state; and a debug state machine responsive to said first output trigger signal to selectively provide a first action signal. | ||
| 地址 | Sunnyvale CA US | ||