| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a CDR circuit which implements detection with a smaller phase detection error while preventing increase of overhead.SOLUTION: The CDR circuit comprises: an AD converter for converting an input signal in accordance with an operation clock; an adder which inputs a second clock of a second frequency that is obtained by adding a first phase to a first clock of a first frequency equal to a symbol rate of the input signal, to the AD converter as an operation clock; a phase detector for detecting a phase included in an output signal of the AD converter; a filter which performs filtering processing on the basis of a second phase detected by the phase detector and a third phase that is outputted by the filter per se, to calculate the third phase; an adder for adding the third phase calculated by the filter and the first phase to calculate a fourth phase; and a determiner which uses the fourth phase calculated by the adder to calculate reproduction data from the output signal of the AD converter. The third phase minimizing a phase error between the second phase and the fourth phase is calculated by a least-square method.</p> |
