| 摘要 |
<p>A flip-flop circuit according to an embodiment of the present invention, which has reduced power consumption, time delay, and area, comprises: a master circuit to receive input data, an input clock signal, and a bypass signal and output an intermediate signal to a first node; and a slave circuit to receive the intermediate signal from the first node, receive the input clock signal and the bypass signal, and output an output clock signal, wherein the slave circuit is controlled by the bypass signal to output one of a buffered input clock signal and a stretch clock signal as the output clock signal based on a logic level of the bypass signal.</p> |
