| 发明名称 |
RECEPTION CIRCUIT |
| 摘要 |
A reception circuit has: a phase detector that detects a phase code based on a phase of data in relation to a first clock signal; a calibration signal generator that, in a calibration mode, adjusts a frequency of the first clock signal or the data so that the phase code detected by the phase detector changes; a calibrator that, in the calibration mode, stores a difference between the phase code and an ideal value of the detected phase, and that, in a normal operation mode, outputs the ideal value in correspondence with the phase code detected by the phase detector; and a phase adjustor that, in the normal operation mode, adjusts a phase of the first clock signal based on the phase code detected by the phase detector and the ideal value, and that outputs to the phase detector. |
| 申请公布号 |
US2015043695(A1) |
申请公布日期 |
2015.02.12 |
| 申请号 |
US201414334761 |
申请日期 |
2014.07.18 |
| 申请人 |
FUJITSU LIMITED |
发明人 |
SUZUKI Shigeto;TAMURA Hirotaka |
| 分类号 |
H04L7/02;H04L7/00;H04B1/16 |
主分类号 |
H04L7/02 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A reception circuit comprising:
a phase detector that detects a phase code based on a phase of data in relation to a first clock signal; a calibration signal generator that, in a calibration mode, adjusts a frequency of the first clock signal or the data so that the phase code detected by the phase detector changes; a calibrator that, in the calibration mode, stores a difference between the phase code detected by the phase detector and an ideal value of the detected phase, and that, in a normal operation mode, outputs the ideal value in correspondence with the phase code detected by the phase detector; and a phase adjustor that, in the normal operation mode, adjusts a phase of the first clock signal based on the phase code detected by the phase detector and the ideal value, and that outputs to the phase detector. |
| 地址 |
Kawasaki-shi JP |
