发明名称 INTER-CHIP MEMORY INTERFACE STRUCTURE
摘要 In an embodiment, a stacked package-on-package system has a memory die and a logic die. The memory die comprises a first memory and a second memory, each operated independently of the other, and each having an inter-chip interface electrically connected to the logic die. The logic die has two independent clock sources, one to provide a first clock signal to the first memory, and the other clock source to provide a second clock signal to the second memory.
申请公布号 KR20150016605(A) 申请公布日期 2015.02.12
申请号 KR20147036817 申请日期 2013.05.31
申请人 发明人
分类号 G06F12/10;G06F13/16;G06F13/42;G11C5/04;G11C5/06;G11C7/10;H01L27/00 主分类号 G06F12/10
代理机构 代理人
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