发明名称 Simulator Apparatus and Method for design of CAN Bus
摘要 <p>The present invention relates to a simulator apparatus and a method thereof. The simulator apparatus of the present invention confirms first delay time which is transmission delay time according to the number of branch lines and the length of the branch line based on a linear division condition and confirms second delay time which is transmission delay time according to the number of the branch lines connected to a joint connector and the length of the branch line connected to the joint connector based on a star shaped division condition. The simulator apparatus searches a combination between the number and the length of the branch line connected to the joint connector when the second delay time is not over the first delay time. The present invention effectively executes a design which is satisfied with the transmission time specification in the linear structure of the standard even if the joint connector is used.</p>
申请公布号 KR101492557(B1) 申请公布日期 2015.02.12
申请号 KR20130004917 申请日期 2013.01.16
申请人 发明人
分类号 G06F17/50;G06F19/00 主分类号 G06F17/50
代理机构 代理人
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