发明名称 アクティブ層の厚み減少を伴う歪トランジスタを形成するための構造歪を与えられた基板
摘要 <p>In a strained SOI semiconductor layer, the stress relaxation which may typically occur during the patterning of trench isolation structures may be reduced by selecting an appropriate reduced target height of the active regions, thereby enabling the formation of transistor elements on the active region of reduced height, which may still include a significant amount of the initial strain component. The active regions of reduced height may be advantageously used for forming fully depleted field effect transistors.</p>
申请公布号 JP5666451(B2) 申请公布日期 2015.02.12
申请号 JP20110524262 申请日期 2009.08.28
申请人 发明人
分类号 H01L21/76;H01L21/336;H01L21/762;H01L21/8234;H01L27/08;H01L27/088;H01L27/12;H01L29/786 主分类号 H01L21/76
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