发明名称 ALLOCATION OF ALIAS REGISTERS IN A PIPELINED SCHEDULE
摘要 In an embodiment, a system includes a processor including one or more cores and a plurality of alias registers to store memory range information associated with a plurality of operations of a loop. The memory range information references one or more memory locations within a memory. The system also includes register assignment means for assigning each of the alias registers to a corresponding operation of the loop, where the assignments are made according to a rotation schedule, and one of the alias registers is assigned to a first operation in a first iteration of the loop and to a second operation in a subsequent iteration of the loop. The system also includes the memory coupled to the processor. Other embodiments are described and claimed.
申请公布号 KR20150016599(A) 申请公布日期 2015.02.12
申请号 KR20147036540 申请日期 2013.05.30
申请人 发明人
分类号 G06F9/38;G06F9/46;G06F13/16 主分类号 G06F9/38
代理机构 代理人
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