SEMICONDUCTOR TEST AND MONITORING STRUCTURE TO DETECT BOUNDARIES OF SAFE EFFECTIVE MODULUS

摘要

A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.

主权项

1. A method of testing an integrated circuit (IC) chip, the method comprising:
providing an IC chip having a plurality of layers, at least two of the plurality of layers being metal layers, wherein the IC chip includes a test structure comprising:
at least one solder bump pad on the IC chip;a solder bump positioned on the at least one solder bump pad; anda monitor chain proximate to the at least one solder bump pad, wherein the monitor chain comprises at least one metal via stack, the at least one metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where the at least one metal via stack is positioned substantially under the solder bump;joining the IC chip to a semiconductor package;performing at least one stress test on the semiconductor package; andobtaining information related to the circuit.