DUAL-PORT POSITIVE LEVEL SENSITIVE DATA RETENTION LATCH

摘要

In an embodiment of the invention, a dual-port positive level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and the control signals SS and SSN. The signals CKT, CLKZ, RET, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.

主权项

1. A dual-port positive level sensitive data retention latch comprising:
a clocked inverter configured to receive a first data bit (D1), clock signal (CKT), clock signal (CLKZ) and a retention mode control signal (RET) wherein (CKT), (CLKZ) and (RET) determine whether the data output (QN) from the clocked inverter is the binary compliment of data bit (D1) or an indeterminate value; a dual-port latch configured to receive the output (QN) of the clocked inverter, a second data bit (D2), the clock signal (CKT), the clock signal (CLKZ), the retain control signal (RET), a latch control signal (SS) and a latch control signal (SSN) wherein signals (CKT), (CLKZ), (RET), SS) and (SSN) determine whether the output (QN) of the clocked inverter or the second data bit (D2) is latched in the dual-port latch.