发明名称 METHOD FOR MICROVIA FILLING BY COPPER ELECTROPLATING WITH THROUGH-SILICON VIA TECHNOLOGY FOR 3D COPPER INTERCONNECT AT HIGH ASPECT RATIO
摘要 A method for microvia filling by copper electroplating with a through-silicon via technology for a 3D copper interconnect at a high aspect ratio. The method comprises: step 1, formulating an electroplating liquid of a copper methyl sulphonate system; step 2, wetting the vias of the through-silicon via technology by means of an electroplating pre-treatment; step 3, introducing same under electrification into a groove and adding a step of tiny current diffusion, so that the copper ions and the additives are rationally distributed at the surface and the interior of the vias of the through-silicon via technology; step 4, connecting the wafer for the through-silicon via technology to the cathode of a power source, fully immersing the electroplating surface of the wafer in the electroplating solution, and electroplating same with a step-by-step current method of rotating or stirring the cathode at a current density of 0.01-10 A/dm2 and a temperature of 15-30°C; and step 5, washing the wafer clean with deionized water, and drying same by spinning or blowing. The method for microvia filling by copper electroplating with a through-silicon via technology for a 3D copper interconnect at a high aspect ratio provided in the present invention has a high via-filling speed, a thin copper layer on the surface, no risk of creating voids and cracks, and can achieve the complete filling of vias having an aspect ratio of more than 10:1 which are extremely difficult to fill.
申请公布号 WO2015017957(A1) 申请公布日期 2015.02.12
申请号 WO2013CN01524 申请日期 2013.12.10
申请人 SHANGHAI SINYANG SEMICONDUCTOR MATERIALS CO., LTD. 发明人 WANG, SU;YU, XIANXIAN;MA, LI;LI, YANYAN
分类号 C25D7/04;C25D3/38;C25D7/12;C25D21/12 主分类号 C25D7/04
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