Transferring architected state between cores

摘要

A method and apparatus for transferring architected state bypasses system memory by directly transmitting architected state between processor cores over a dedicated interconnect. The transfer may be performed by state transfer interface circuitry with or without software interaction. The architected state for a thread may be transferred from a first processing core to a second processing core when the state transfer interface circuitry detects an error that prevents proper execution of the thread corresponding to the architected state. A program instruction may be used to initiate the transfer of the architected state for the thread to one or more other threads in order to parallelize execution of the thread or perform load balancing between multiple processor cores by distributing processing of multiple threads.

主权项

1. A method of transferring state information, comprising:
gathering at least a first portion and a second portion of state information associated with a thread executing within a source processing core, where said first portion of state information is stored in registers and said second portion of state information is stored in other local memory associated with the source processing core; broadcasting the first and second portions of the state information directly from the source processing core to a plurality of target processing cores over a dedicated interconnect that bypasses any memory shared between the source processing core and the target processing cores; storing, by each of the target processing cores, the first and second portions of the state information; and executing, by each of the target processing cores while the first thread executes on the source processing core, a second thread on the target processing core based on said portions of the state information, each of the second threads being a clone of the first thread.