Low cost anti-fuse structure

摘要

An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier liner separates the first conductive metal from any portion of the interconnect dielectric material. The anti-fuse structure is laterally adjacent an interconnect structure that is formed within the same interconnect dielectric material as the anti-fuse structure.

主权项

1. A semiconductor structure comprising:
an interconnect dielectric material having at least one opening located therein, said at least one opening extends from a topmost surface of said interconnect dielectric material to a bottommost surface of said interconnect dielectric material; and an anti-fuse structure located within the least one opening, wherein the anti-fuse structure comprises:
a diffusion barrier liner located within the at least one opening and in direct contact with at least sidewall surfaces of the interconnect dielectric material and having a bottommost horizontal surface that is coplanar with said bottommost surface of said interconnect dielectric material;a first conductive metal plug located within the at least one opening and located on an exposed surface of the diffusion barrier liner, wherein said first conductive metal plug includes vertical sidewall portions that extend upward from an uppermost surface of the first conductive metal plug;an anti-fuse material liner located on an exposed surface of the first conductive metal plug and an exposed surface of the vertical sidewall portions; anda second conductive metal plug located on an exposed surface of the anti-fuse material liner, wherein each of the diffusion barrier liner, the vertical sidewall portions, the anti-fuse material liner, and the second conductive metal plug have an uppermost surface that is co-planar with an uppermost surface of the interconnect dielectric material.