Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements

摘要

A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

主权项

1. A method for manufacturing a chip arrangement, the method comprising:
forming a hole in a carrier comprising at least one chip, wherein forming a hole in the carrier comprises:
selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material;selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall, wherein forming the hole in the carrier comprises forming the hole through the carrier wherein the at least one chip is separated from the carrier, and wherein the at least one cavity side wall comprises a side wall of the at least one chip; the method further comprising subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.