Nonvolatile semiconductor memory device and read method for the same

摘要

A cross point nonvolatile memory device capable of suppressing sneak-current-caused reduction in sensitivity of detection of a resistance value of a memory element is provided. The device includes perpendicular bit and word lines; a cross-point cell array including memory cells each having a resistance value reversibly changing between at least two resistance states according to electrical signals, arranged on cross-points of the word and bit lines; an offset detection cell array including an offset detection cell having a resistance higher than that of the memory cell in a high resistance state, the word lines being shared by the offset detection cell array; a read circuit (a sense amplifier) that determines a resistance state of a selected memory cell based on a current through the selected bit line; and a current source which supplies current to the offset detection cell array in a read operation period.

主权项

1. A nonvolatile semiconductor memory device, comprising:
word lines formed in parallel in a first plane; bit lines formed in parallel in a second plane and three-dimensionally crossing the word lines, the second plane being parallel to the first plane; a first cross-point cell array including first type cells located at three-dimensional cross-points of the word lines and the bit lines; one or more dummy bit lines formed in parallel and three-dimensionally crossing the word lines in the second plane; a second cross-point cell array including cells, each of which is either the first type cell or a second type cell, located at a corresponding one of three-dimensional cross-points of the word lines and the one or more dummy bit lines, the second cross-point cell array including at least one each of the first type cells and the second type cells for each of the one or more dummy bit lines; a word line selection circuit that selects one of the word lines as a selected word line; a bit line selection circuit that selects one of the bit lines as a selected bit line; a dummy bit line selection circuit that selects at least one of the one or more dummy bit lines as a selected dummy bit line; a read circuit that applies a predetermined voltage via the selected word line and the selected bit line to a selected cell which is a corresponding first type cell in the first cross-point cell array, and determines a resistance state of the selected cell based on a current which flows through the selected bit line; and a current source that supplies a current to the second cross-point cell array via the selected dummy bit line in a period of a read operation performed by the read circuit, wherein the first type cell includes a variable resistance element that operates as a memory by reversibly changing between at least two resistance states based on an electrical signal applied between a corresponding one of the word lines and a corresponding one of the bit lines, the second type cell includes an offset detection cell having a resistance value that is, irrespective of an electrical signal applied between a corresponding one of the word lines and a corresponding one of the one or more dummy bit lines, higher than the resistance value of the variable resistance element in a high resistance state which is a state of the variable resistance element when operating as the memory, and the dummy bit line selection circuit selects, as the selected dummy bit line, a dummy bit line such that the second type cell is disposed at a three-dimensional cross-point of the selected dummy bit line and the selected word line, in a period of a read operation performed by the read circuit.