CMOS three-dimensional image sensor detectors having reduced inter-gate capacitance, and enhanced modulation contrast

摘要

A CMOS detector with pairs of interdigitated elongated finger-like collection gates includes p+ implanted regions that create charge barrier regions that can intentionally be overcome. These regions steer charge to a desired collection gate pair for collection. The p+ implanted regions may be formed before and/or after formation of the collection gates. These regions form charge barrier regions when an associated collection gate is biased low. The barriers are overcome when an associated collection gate is high. These barrier regions steer substantially all charge to collection gates that are biased high, enhancing modulation contrast. Advantageously, the resultant structure has reduced power requirements in that inter-gate capacitance is reduced in that inter-gate spacing can be increased over prior art gate spacing and lower swing voltages may be used. Also higher modulation contrast is achieved in that the charge collection area of the low gate(s) is significantly reduced.

主权项

1. A CMOS-implementable sensor that generates charge responsive to detected photon energy, the sensor comprising:
a semiconductor structure; at least one biasable gate disposed on an upper surface of said semiconductor structure; a doping barrier region, formed in said semiconductor underlying said gate; wherein when a bias voltage VG is coupled to said biasable gate having bias voltage magnitude VRELEASE