| 发明名称 | Methods and systems for calibration of a delay locked loop | ||
| 摘要 | A method for calibrating a delay locked loop (“DLL”) having a plurality of delay segments, comprises: determining segment delay values for the delay segments; calculating a full-cycle delay value for an input signal to the DLL; adjusting one or more of the segment delay values as a function of the full-cycle delay value to generate one or more adjusted delay values; and calculating weights for the delay segments as a function of the segment delay values, the full-cycle delay, and the one or more adjusted delay values, wherein the weights are used to calibrate the DLL. | ||
| 申请公布号 | US8952737(B2) | 申请公布日期 | 2015.02.10 |
| 申请号 | US201314065754 | 申请日期 | 2013.10.29 |
| 申请人 | Kool Chip, Inc. | 发明人 | Mishra Kishore;Mohanty Purna C.;Rao Venkata N. S. N. |
| 分类号 | H03L7/06;H03L7/00 | 主分类号 | H03L7/06 |
| 代理机构 | Venture Pacific Law, PC | 代理人 | Venture Pacific Law, PC |
| 主权项 | 1. A method for calibrating a delay locked loop (“DLL”) having a plurality of delay segments, comprising: determining segment delay values for the delay segments; calculating a full-cycle delay value for an input signal to the DLL; adjusting one or more of the segment delay values as a function of the full-cycle delay value to generate one or more adjusted delay values; and calculating weights for the delay segments as a function of the segment delay values, the full-cycle delay, and the one or more adjusted delay values, wherein the weights are used to calibrate the DLL. | ||
| 地址 | San Jose CA US | ||