Memory with termination circuit

摘要

Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.

主权项

1. A semiconductor device on a chip and for use with a memory device, the semiconductor device comprising:
an external data terminal configured to be coupled to the memory device via a signal line and configured to receive a first set of burst data from the memory device and to receive a second set of burst data from the memory device after an interval; a termination circuit coupled to the external data terminal; a buffer circuit having an input coupled to the external data terminal; and a control circuit configured to provide to the termination circuit a control signal having one of a first level for activating the termination circuit and a second level for deactivating the termination circuit,
the control circuit configured to provide the control signal having the first level to the termination circuit so that the termination circuit is activated from a start of receiving the first set of burst data until an end of receiving the second set of burst data if the interval is determined to be less than or equal to a threshold, andthe control circuit configured to provide the control signal having the second level to the termination circuit so that the termination circuit is deactivated from an end of receiving the first set of burst data until a start of receiving the second set of burst data if the interval is determined to exceed the threshold.