发明名称 |
Super-self-aligned contacts and method for making the same |
摘要 |
A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number of second hard mask filaments are formed adjacent to each side surface of each first hard mask portion. A width of each second hard mask filament is set to define an active area contact-to-gate structure spacing. A first passage is etched between facing exposed side surfaces of a given pair of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area. A second passage is etched through a given first hard mask portion and through a depth of the semiconductor wafer to a top surface of the underlying gate structure. An electrically conductive material is deposited within both the first and second passages to respectively form an active area contact and a gate contact. |
申请公布号 |
US8951916(B2) |
申请公布日期 |
2015.02.10 |
申请号 |
US201314033952 |
申请日期 |
2013.09.23 |
申请人 |
Tela Innovations, Inc. |
发明人 |
Smayling Michael C. |
分类号 |
H01L21/467;H01L21/768;H01L21/8234;H01L21/311;H01L29/49 |
主分类号 |
H01L21/467 |
代理机构 |
Martine Penilla Group, LLP |
代理人 |
Martine Penilla Group, LLP |
主权项 |
1. A method for fabricating an active area contact within a semiconductor wafer, comprising:
forming a number of first hard mask portions over a corresponding number of underlying gate structures such that each first hard mask portion vertically shadows a respective one of the underlying gate structures; forming a number of second hard mask filaments adjacent to each of the number of first hard mask portions such that a combined width of each first hard mask portion and its adjoining second hard mask filaments is greater than a width of the respective underlying gate structure, and such that a width of each second hard mask filament defines an active area contact-to-gate structure spacing; etching a passage between facing surfaces of neighboring second hard mask filaments and through a depth of the semiconductor wafer to an active area; and depositing an electrically conductive material within the passage to form the active area contact. |
地址 |
Los Gatos CA US |