发明名称 |
Multiscale modulus filter bank and applications to pattern detection, clustering, classification and registration |
摘要 |
A digital filter bank having a number J≧1 of stages is disclosed. For each integer j such that 1≦j≦J, the j-th stage includes a plurality of filtering units (20, 21) each receiving an input signal of the j-th stage. These filtering units include a low-pass filtering unit (20) using real filtering coefficients and at least one band-pass filtering unit (21) using complex filtering coefficients. Following each band-pass filtering unit of the j-th stage, a respective modulus processing unit (25) generates a processed real signal as a function of squared moduli of complex output values of the band-pass filtering unit. The input signal of the first stage is a digital signal supplied to the digital filter bank, while for 1<j≦J, the input signal of the j-th stage includes the processed real signal generated by at least one modulus processing unit of the (j−1)-th stage. |
申请公布号 |
US8953875(B2) |
申请公布日期 |
2015.02.10 |
申请号 |
US201113698169 |
申请日期 |
2011.05.26 |
申请人 |
Ecole Polytechnique |
发明人 |
Mallat Stephane |
分类号 |
G06K9/00;G06K9/46;G06K9/52 |
主分类号 |
G06K9/00 |
代理机构 |
Young & Thompson |
代理人 |
Young & Thompson |
主权项 |
1. A digital filter bank having a number J of stages, where J is an integer greater than one, wherein for each integer j such that 1≦j≦J, the j-th stage comprises:
a plurality of filtering units each receiving an input signal of the j-th stage, including a low-pass filtering unit and at least one band-pass filtering unit using complex filtering coefficients; and following each band-pass filtering unit of the j-th stage, a respective modulus processing unit for generating a processed real signal as a function of squared moduli of complex output values of said band-pass filtering unit,wherein the input signal of the first stage is a digital signal supplied to the digital filter bank, and wherein for 1<j≦J, the input signal of the j-th stage includes the processed real signal generated by at least one modulus processing unit of the (j−1)-th stage. |
地址 |
Palaiseau FR |