Germanium oxide free atomic layer deposition of silicon oxide and high-k gate dielectric on germanium containing channel for CMOS devices

摘要

A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.

主权项

1. A semiconductor device comprising:
a substrate comprising a germanium containing region and an adjoining silicon containing region, wherein an upper surface of said germanium containing region is coplanar with an upper surface of said silicon containing region; a first gate structure on a channel region of said germanium containing region and comprising:
a first silicon oxide layer that is in direct contact with an upper surface of said germanium containing region, a second silicon oxide layer of a substantially uniform thickness having a 1 sigma non-uniformity of less than 0.2 Å that is in direct contact with said first silicon oxide layer, at least one first high-k gate dielectric layer in direct contact with said second silicon oxide layer, and at least one first gate conductor in direct contact with said at least one first high-k gate dielectric layer, wherein said upper surface of said germanium containing region is substantially free of germanium oxide, and a source region and a drain region on opposing sides of said channel region of said germanium containing region; and a second gate structure on a channel region of said silicon containing region and comprising:
a first silicon oxide layer that is in direct contact with an upper surface of said silicon containing region, a second silicon oxide layer of a substantially uniform thickness having a 1 sigma non-uniformity of less than 0.2 Å that is in direct contact with said first silicon oxide layer, at least one second high-k gate dielectric layer in direct contact with said second silicon oxide layer, and at least one second gate conductor in direct contact with said at least one second high-k gate dielectric layer, and a source region and a drain region on opposing sides of said channel region of said silicon containing region.