Integrated DRAM memory device

摘要

A DRAM memory device includes at least one memory cell including a transistor having a first electrode, a second electrode and a control electrode. A capacitor is coupled to the first electrode. At least one electrically conductive line is coupled to the second electrode and at least one second electrically conductive line is coupled to the control electrode. The electrically conductive lines are located between the transistor and the capacitor. The capacitor can be provided above a fifth metal level.

主权项

1. An integrated circuit, comprising:
a DRAM memory device comprising at least one memory cell, wherein the memory cell includes a transistor having a first electrode, a second electrode and a control electrode, and further including a capacitor coupled to said first electrode, wherein at least a first electrically conducting line having a width and length is coupled to the second electrode, and wherein at least a second electrically conducting line having a width and a length is coupled to the control electrode, wherein first and second electrically conducting lines are placed within the integrated circuit between the transistor and the capacitor, wherein the length of each first electrically conducting line principally extends in a first direction, wherein the length of each second electrically conducting line principally extends in a second direction, and wherein an active region containing the first and second electrodes of the transistor has a width and a length, and the length of the active region principally extends in a third direction different from the first and second directions.