发明名称 Semiconductor devices having encapsulated stressor regions and related fabrication methods
摘要 Apparatus and related fabrication methods are provided for semiconductor device structures having silicon-encapsulated stressor regions. One semiconductor device includes a semiconductor substrate, a gate structure overlying the semiconductor substrate, stressor regions formed in the semiconductor substrate proximate the gate structure, and a silicon material overlying the stressor regions, the silicon material encapsulating the stressor regions.
申请公布号 US8951873(B2) 申请公布日期 2015.02.10
申请号 US201313785480 申请日期 2013.03.05
申请人 GLOBALFOUNDRIES, Inc. 发明人 Flachowsky Stefan;Hoentschel Jan
分类号 H01L21/336;H01L29/78;H01L29/165;H01L29/66 主分类号 H01L21/336
代理机构 Ingrassia Fisher & Lorenz, P.C. 代理人 Ingrassia Fisher & Lorenz, P.C.
主权项 1. A semiconductor device comprising: a semiconductor substrate comprising a first material having a first etch rate and a first oxidation rate; a gate structure overlying the semiconductor substrate; a channel region in the semiconductor substrate and underneath the gate structures; stressor regions formed in the semiconductor substrate proximate the gate structure and directly adjacent to the channel region comprising a second material having a second etch rate that is different from the first etch rate and a second oxidation rate that is different from the first oxidation rate, wherein the stressor regions have a thickness in a direction perpendicular to a top surface of the semiconductor substrate that is greatest directly adjacent to the channel region and that decreases in thickness with increasing distance from the channel region in a direction parallel to the top surface of the semiconductor substrate; and a silicon material overlying an entirety the stressor regions and comprising a third material having the first etch rate and the first oxidation rate, the silicon material fully encapsulating the stressor regions, wherein an entirety of a top surface of the silicon material overlying the stressor regions and the top surface of the semiconductor substrate underneath the gate structure are co-planar with respect to one another.
地址 Grand Cayman KY