Multi-stage command processing pipeline and method for shared cache access

摘要

A command processing pipeline is coupled to a shared cache. The command processing pipeline comprises (i) a first command processing stage configured to sequentially receive and process first and second cache commands, and (ii) a second command processing stage coupled to the first command processing stage. The first and the second command processing stages are two consecutive command processing stages of the command processing pipeline. The first and second command processing stages may access different groups of cache resources, and the first and second cache commands may be processed during consecutive clock cycles of a clock signal. Processing of the second cache command may be performed independently of an outcome of processing the first cache command by the first command processing stage. A third command processing stage may write data associated with the first cache command to one of a valid memory and a data memory included in the cache.

主权项

1. A command processing pipeline configured to be coupled to a shared cache, the command processing pipeline comprising:
a first command processing stage configured to perform a comparison, in a first clock cycle, of an address associated with a first cache command to addresses stored in the cache; a second command processing stage configured to, in a second clock cycle, (i) receive the first cache command from the first command processing stage, and (ii) based on a result of the comparison, process the first cache command by one or more of (A) providing a read access to one or both of a data memory and an error correcting code memory included in the cache, (B) providing a write access to one or both of the data memory and the error correcting code memory included in the cache, and (C) generating an error correcting code associated with data to be written to the data memory; and a third command processing stage configured to, in a third clock cycle, (i) receive the first cache command from the second command processing stage, and (ii) process the first cache command by writing data associated with the first cache command to one of a valid memory and a dirty memory included in the cache, the valid memory and the dirty memory being different from the data memory.