Storage subsystem

摘要

Provided is a storage subsystem capable of speeding up the input/output processing for a cache memory. Microprocessor Packages manage information related to a VDEV ownership for controlling virtual devices and a cache segment ownership for controlling cache segments in units of Microprocessor Packages, and one Microprocessor among multiple Microprocessors belonging to the determined Microprocessor Package to perform input/output processing for the virtual devices searches cache control information stored in the Package Memory without searching the cache control information in the shared memory, and if data exists in the cache memory, accesses the cache memory, and if it does not, accesses the virtual devices.

主权项

1. A storage system coupled to one or more host computers, comprising:
a switch; a plurality of storage devices providing a plurality of virtual devices to the host computers; a plurality of first interfaces coupled to the switch and the host computers; a plurality of second interfaces coupled to the switch and the storage devices; a plurality of processor packages coupled to the switch, each of the processor packages comprise one or more processors and a memory which is only accessed by the processors therein, each of the processors executing input/output processes to one or more of the virtual devices; a cache memory coupled to the switch which temporarily stores data associated with the input/output process by the processor packages, the cache memory including a plurality of cache areas; and a shared memory coupled to the switch which stores control information including cache control information used for accessing the cache memory, the control information being shared by all the processors of the processor packages, wherein the memory in each of the processor packages stores the cache control information, wherein each of the processor packages manages information related to a first owner right allocated thereto for indicating possession of an access right to one or more of the plurality of virtual devices, and a second owner right allocated thereto for indicating possession of an access right to one or more of the cache areas in the cache memory, the first owner right permitting a particular processor package to access a particular one or more virtual devices while excluding other processor packages from accessing the particular one or more virtual devices, and the second owner right permitting the particular processor package to access a particular one or more cache areas while excluding other processor packages from accessing the particular one or more cache areas, wherein, if the first interface receives an input/output request from one of the host computers to one of the virtual devices, the first interface transfers the input/output request to a first processor package having the first owner right to the virtual device to which the input/output request is directed, wherein the first processor package executes processing of the input/output request by accessing one or more of the cache areas to which the processor package has the second owner right thereto, by referring to the cache control information in the memory therein, wherein if the cache control information in the memory therein is updated with the processing, the cache control information in the shared memory is updated accordingly, wherein if the first owner right of one of the virtual devices is transferred from one of the processor packages to another of the processor packages, the another of the processor packages reflects the cache control information related to the one of the virtual devices in the shared memory to the cache control information in the memory of the another of the processor packages, wherein a hit ratio showing that there is data in the cache area of the cache memory is calculated for each of the plurality of processor packages, and wherein, if a difference in the hit ratio of each processor package exceeds a prescribed threshold value, the second owner right of the cache area handled by a processor package with a high hit ratio is changed by being allocated to a processor package with a low hit ratio.