Memory address translation-based data encryption with integrated encryption engine

摘要

A method and circuit arrangement utilize an integrated encryption engine within a processing core of a multi-core processor to perform encryption operations, i.e., encryption and decryption of secure data, in connection with memory access requests that access such data. The integrated encryption engine is utilized in combination with a memory address translation data structure such as an Effective To Real Translation (ERAT) or Translation Lookaside Buffer (TLB) that is augmented with encryption-related page attributes to indicate whether pages of memory identified in the data structure are encrypted such that secure data associated with a memory access request in the processing core may be selectively streamed to the integrated encryption engine based upon the encryption-related page attribute for the memory page associated with the memory access request.

主权项

1. A method of accessing data in a data processing system, the method comprising:
in response to a memory access request initiated by a thread in a processing core disposed in a multi-core processor, accessing an encryption-related page attribute in a memory address translation data structure to determine whether a memory page associated with the memory access request is encrypted, wherein the memory address translation data structure is configured to perform memory address translation between virtual and real memory addresses; and streaming secure data in the memory page through a hardware-based encryption engine integrated into the processing core in response to determining that the memory page associated with the memory access request is encrypted.