Semiconductor integrated circuit capable of controlling read command

摘要

The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode.

主权项

1. A semiconductor integrated circuit comprising:
a command decoder configured to provide a write command and to provide a read command; a read/write command controller configured to provide a write-read clock in synchronization with a first edge of a clock when the write command is activated, and provide the write-read clock in synchronization with a second edge of the clock when the read command is activated; and a column address latch unit configured to latch a column address in response to a burst write-read command generated from the write-read clock and a burst signal.