Silicon carbide semiconductor device and its manufacturing method

摘要

A silicon carbide vertical MOSFET having low ON-resistance and high blocking voltage. A first deposition film of low concentration silicon carbide of a first conductivity type is formed on the surface of a high concentration silicon carbide substrate of a first conductivity type. Formed on the first deposition film is a second deposition film that includes a high concentration gate region of a second conductivity type, with a first region removed selectively. A third deposition film is formed on the second deposition film, which includes a second region that is wider than the selectively removed first region, a high concentration source region of a first conductivity type, and a low concentration gate region of a second conductivity type. A low concentration base region of a first conductivity type is formed in contact with the first deposition film in the first and second regions.

主权项

1. A silicon carbide semiconductor device, comprising:
a lower deposition film which is formed of a single layer of silicon carbide of a first conductivity type, and which has lower impurity concentration than a high impurity concentration silicon carbide substrate of the first conductivity type and which is formed on a surface of the silicon carbide substrate; a high impurity concentration gate region of a second conductivity type selectively formed across from an upper surface to an interior of the lower deposition film, the high impurity concentration gate region being adjacent to and in contact with a non-implanted portion that is an exposed part of the upper surface of the lower deposition film; an upper deposition film formed on the lower deposition film in which the high impurity concentration gate region is formed, wherein the upper deposition film comprises:
a low impurity concentration gate region of the second conductivity type directly deposited on a surface of the high impurity concentration gate region of the second conductivity type and having a lower impurity concentration than the high impurity concentration gate region;a high impurity concentration source region of the first conductivity type selectively formed on part of an upper surface of the low impurity concentration gate region of the second conductivity type and being more heavily doped than the low impurity concentration gate region of the second conductivity type; anda low impurity concentration base region of the first conductivity type directly on the non-implanted portion and having a greater width than the non-implanted portion,wherein the non-implanted portion is doped with nitrogen at a concentration of 5×1015 cm−3, and the low impurity concentration base region is doped with nitrogen at a concentration of 1×1016 cm−3;wherein the high impurity concentration source region is not adjacent to the high impurity concentration gate region by the low impurity concentration gate region; and wherein the high impurity concentration gate region extends to directly contact the low impurity concentration base region; and further comprising: a gate insulation film formed on at least a surface of the upper deposition film; a gate electrode formed via the gate insulation film; a drain electrode having a low-resistance contact connection with a backside of the silicon carbide substrate of the first conductivity type; and a source electrode having a low-resistance contact connection with part of the high impurity concentration source region of the first conductivity type and the low impurity concentration gate region of the second conductivity type.