COMPACT THREE DIMENSIONAL VERTICAL NAND AND METHOD OF MAKING THEREOF

摘要

A NAND device has at least a 3×3 array of vertical NAND strings in which the control gate electrodes are continuous in the array and do not have an air gap or a dielectric filled trench in the array. The NAND device is formed by first forming a lower select gate level having separated lower select gates, then forming plural memory device levels containing a plurality of NAND string portions, and then forming an upper select gate level over the memory device levels having separated upper select gates.

主权项

1. A method of making an array of monolithic three dimensional vertical NAND strings, comprising:
forming a lower select gate level over a substrate, the lower select gate level comprising lower portions of a plurality of semiconductor channels, a plurality of lower source or drain electrodes, each lower source or drain electrode electrically connected to each of the plurality of lower portions of the semiconductor channels, and a plurality of lower select gate electrodes, each lower select gate electrode located adjacent to a gate dielectric contacting the lower portion of each semiconductor channel; after the step of forming a lower select gate level, forming a plurality of memory device levels over the lower select gate level, wherein the memory device levels comprise a plurality of NAND string portions; and forming an upper select gate level over the plurality of memory device levels, the upper select gate level comprising upper portions of a plurality of semiconductor channels, a plurality of upper source or drain electrodes, each upper source or drain electrode electrically connected to each of the plurality of upper portions of the semiconductor channels, and a plurality of upper select gate electrodes, each upper select gate electrode located adjacent to a gate dielectric contacting the upper portion of each semiconductor channel.