| 发明名称 |
VIA STRUCTURE FOR THREE-DIMENSIONAL CIRCUIT INTEGRATION |
| 摘要 |
Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer. Each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer. The landing pads are coupled by a single conductive via and are aligned in a stack of the bottom layer and the upper layers such that each of the landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount. |
| 申请公布号 |
US2015035169(A1) |
申请公布日期 |
2015.02.05 |
| 申请号 |
US201414518704 |
申请日期 |
2014.10.20 |
| 申请人 |
International Business Machines Corporation |
发明人 |
Farooq Mukta G.;Graves-Abe Troy L.;Skordas Spyridon;Winstel Kevin R. |
| 分类号 |
H01L23/00;H01L23/538;H01L27/06 |
主分类号 |
H01L23/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A circuit incorporating three-dimensional integration (3Di) comprising:
a bottom layer including a bottom landing pad connected to functional components in the bottom layer; and a plurality of upper layers, stacked above the bottom layer, wherein each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer, wherein the upper and bottom landing pads are coupled by a single conductive via and wherein the upper and bottom landing pads are aligned in a stack of the bottom layer and the upper layers such that each of the upper and bottom landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount. |
| 地址 |
Armonk NY US |
