SPLIT GATE NON-VOLATILE MEMORY CELL

摘要

A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension.

主权项

1. A method of making a semiconductor structure using a substrate having a background doping of a first conductivity type, comprising:
forming a gate structure comprising a gate dielectric on the substrate and a select gate layer on the gate dielectric, wherein the gate layer has a first end; implanting a first portion of the substrate adjacent to the first end with dopants of a second conductivity type using the first end as a mask, wherein the implanting is prior to any dopants being implanted into the background doping of the first portion and wherein the first portion becomes a first doped region of the second conductivity type; forming a non-volatile memory gate structure comprising a select gate of the select gate layer, a storage layer having a first portion over the first doped region, and a control gate over the storage layer, wherein the select gate has a first side as the first end and a second side opposite the first side, wherein the storage layer has a second portion between the first side of the select gate and a first side of the control gate; implanting at a non-vertical angle with dopants of the first conductivity type to form a deep doped region under substantially all of the select gate; and implanting with dopants of the second conductivity type to from a source/drain extension in the substrate substantially aligned with the second side of the select gate.