Semiconductor Device and Fabricating the Same

摘要

The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, and source/drain regions respectively. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the first gate region to form first outer oxide layer and inner nanowire set, and exposing the first inner nanowire set. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire set. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, and exposing the second inner nanowire set. A second HK/MG stack wraps around the second inner nanowire set.

主权项

1. A method for fabricating an integrated circuit device, the method comprising:
providing a precursor, the precursor including:
a substrate having first and second metal-oxide-semiconductor (MOS) regions;first gate and source/drain regions formed in the first MOS region, the first gate region including a semiconductor layer stack; andsecond gate and source/drain regions formed in the second MOS region, the second gate region including the semiconductor layer stack,wherein the semiconductor layer stack includes a first layer of a first semiconductor material, a second layer of a second semiconductor material disposed over the first layer, and a third layer of the first semiconductor material disposed over the second layer, wherein the first semiconductor material is different than the second semiconductor material; laterally exposing the semiconductor layer stack in the first gate region; oxidizing the first, second, and third layers of the semiconductor layer stack in the first gate region to form a first outer oxide layer and a first inner nanowire set, a first nanowire in the first inner nanowire set extending from the first source region to the corresponding first drain region; removing the first outer oxide layer to expose the first inner nanowire set in the first gate region; forming a first high-k/metal gate (HK/MG) stack wrapping around the first inner nanowire set; laterally exposing the semiconductor layer stack in the second gate region; oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, a second nanowire in the second inner nanowire set extending from the second source region to the corresponding second drain region; removing the second outer oxide layer to expose the second inner nanowire set in the second gate region; and forming a second HK/MG stack wrapping around the second inner nanowire set.