| 摘要 |
The present invention relates to a processor and a memory. More specifically, the present invention relates to a switchable on chip memory accessible by various master intellectual properties (IPs) and a method for controlling the same, and the method for controlling the on chip memory, according to one embodiment of the present invention, can comprise the steps of: setting memory allocation information including at least one among modes of respective master IPs, priority, space size of a required memory, and correlation with other master IPs; and allocating memories for the respective master IPs by using the memory allocation information. According to the one embodiment of the present invention, various master IPs within an embedded SoC are capable of utilizing all of the advantages of an on chip buffer and an on chip cache. |
