发明名称 SEQUENTIAL DELAY ANALYSIS BY PLACEMENT ENGINES
摘要 Some embodiments provide a method of designing an integrated circuit (IC). The design is expressed as a graph that includes several nodes that represent several IC components. The nodes include a first set of nodes that represent a set of clocked elements. The method creates a second set of nodes by removing all nodes in the first set from the nodes that represent the IC components. The method identifies a set of edges that connect two nodes in the second set without encompassing a third node in the second set. The method assigns an event time to each node in the second set. The method assigns a cost function based on the event times of the nodes connected by each edge and the number of nodes in the first set encompassed by each edge. The method optimizes the cost function and places the components based on the cost function optimization.
申请公布号 US2015040094(A1) 申请公布日期 2015.02.05
申请号 US201414461290 申请日期 2014.08.15
申请人 Tabula, Inc. 发明人 Caldwell Andrew;Teig Steven
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址 Santa Clara CA US