MILLIMETER WAVE WAFER LEVEL CHIP SCALE PACKAGING (WLCSP) DEVICE AND RELATED METHOD

摘要

Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad.

主权项

1. A method of tuning a wafer level chip scale package (WLCSP) structure, the method comprising:
providing the WLCSP structure including:
a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane, wherein the PCB ground plane includes an opening;a set of ground contact devices each contacting the printed circuit board trace connection;a set of chip pads contacting each of the ground contact devices in the set of contact devices;a chip ground plane connecting the set of chip pads, the chip ground plane including an opening; anda signal interconnect interposed between two of the set of ground contact devices, the signal interconnect including:
a signal trace connection electrically isolated from the PCB ground plane;a signal contact device contacting the signal trace connection;a chip pad contacting the signal contact device; anda signal trace connection on a chip contacting the chip pad; determining a performance parameter of the WLCSP structure; and tuning a size of at least one of the opening in the PCB ground plane or the opening in the chip ground plane based upon the determined performance parameter.