METHODS, APPARATUS, INSTRUCTIONS AND LOGIC TO PROVIDE VECTOR SUB-BYTE DECOMPRESSION FUNCTIONALITY

摘要

Methods, apparatus, instructions and logic provide SIMD vector sub-byte decompression functionality. Embodiments include shuffling a first and second byte into the least significant portion of a first vector element, and a third and fourth byte into the most significant portion. Processing continues shuffling a fifth and sixth byte into the least significant portion of a second vector element, and a seventh and eighth byte into the most significant portion. Then by shifting the first vector element by a first shift count and the second vector element by a second shift count, sub-byte elements are aligned to the least significant bits of their respective bytes. Processors then shuffle a byte from each of the shifted vector elements' least significant portions into byte positions of a destination vector element, and from each of the shifted vector elements' most significant portions into byte positions of another destination vector element.

主权项

1. A processor comprising:
a decode stage to decode a first instruction specifying a vector sub-byte decompression operation, a destination vector of byte elements, a source of sub-byte elements and a sub-byte element size; and one or more execution units, responsive to the decoded first instruction, to:
shuffle from the source, a first two bytes containing a first sub-byte element of a first bit alignment into a least significant portion of a first vector element, and a second two bytes containing a second sub-byte element of the same first bit alignment into a most significant portion of the first vector element;shuffle from the source, a third two bytes containing a third sub-byte element of a second bit alignment into a least significant portion of a second vector element, and a fourth two bytes containing a fourth sub-byte element of the same second bit alignment into a most significant portion of the second vector element;shift the first vector element by a first shift count and the second vector element by a second shift count to align the sub-byte elements to a least significant bit of their respective bytes; andshuffle a byte from each of the shifted first and second vector elements' least significant portions into a first destination vector element and from each of the shifted first and second vector elements' most significant portions into a second destination vector element to at least partially restore their original sub-byte order.