PROGRAMMABLE DELAY CIRCUIT

摘要

A computing circuit that includes clocked circuitry, a controller, and a clock generator. The clocked circuitry is configured to receive data and to perform data manipulation on the data based on a first clock signal. The controller is configured to control the transmission of the data to the clocked circuitry. The clock generator is configured to receive as inputs a second clock signal and a delay control signal from the controller, and to delay the second clock signal to generate the first clock signal. The clock generator includes a main delay component configured to receive the second clock signal and to output the first clock signal. The clock generator also includes a switchable delay component connected in parallel with the main delay component, where the switchable delay component is configured to receive as an input the delay control signal from the controller.

主权项

1. A computing circuit, comprising:
clocked circuitry configured to receive data and perform data manipulation on the data based on a first clock signal; a controller configured to control the transmission of the data to the clocked circuitry; and a clock generator configured to receive as inputs a second clock signal and a delay control signal from the controller, and configured to delay the second clock signal to generate the first clock signal, the clock generator comprising: a main delay component configured to receive the second clock signal and output the first clock signal; and a switchable delay component connected in parallel with the main delay component, the switchable delay component configured to receive as an input the delay control signal from the controller.