发明名称 MULTI-VALUE LOGIC MEANS HAVING SYNCHRONIZATION LATCHING FUNCTION, MULTI-VALUE HAZARD REMOVAL MEANS, MULTI-VALUE LOGIC MEANS, AND NUMERICAL VALUE DISCRIMINATION MEANS
摘要 <p>PROBLEM TO BE SOLVED: To provide synchronization type multi-value logic means capable of suppressing its input side overshooting and the like.SOLUTION: Synchronous type multi-value logic means based on a multi-value logic "Hooji algebra" born in Japan is composed of: (multi-value) numerical value discrimination means comprising transistors 81-85 and diodes 86-88 and the like; a D-type flip-flop 127 (having a power supply voltage twice as high as a normal one) operating based on a discrimination result signal from the discrimination means and "a synchronization signal supplied from synchronous signal supply means comprising synchronization signal generation means 60, a transistor 61, and the like"; on-off drive means operating based on an output signal Q of the D-type flip-flop and comprising transistors 22-25; and bi-directional pull-switching means on/off-driven by the on-off drive means and comprising transistors 3 and 5. Further, to the synchronous type multi-value logic means, self-hold switching means comprising transistors 79-84 and the like is added (as a countermeasure against multi-value hazard by input voltage vibration, and a part of its configuration is shared.)</p>
申请公布号 JP2015026878(A) 申请公布日期 2015.02.05
申请号 JP20130144540 申请日期 2013.07.10
申请人 SUZUKI TOSHIYASU 发明人 SUZUKI TOSHIYASU
分类号 H03K19/20 主分类号 H03K19/20
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